Pin-compatible alternates

Find replacement parts for the selected component, scored against the verified gold model — footprint, interfaces, supply range, and abs-max. Drop-ins are safe swaps; “review” needs a firmware or layout change; blocked parts fail a hard constraint.

Candidates

Pick a part and run the finder.

Pin-mux planner

Declare the interfaces your board needs; the planner assigns each to conflict-free physical pins from the verified pinout and emits a locked pin-map (CSV + Zephyr pinctrl). It flags real hazards — pins shared with SWD/JTAG, crystals, or reset, and analog-only pins asked to carry a digital function — and reports anything it can't place rather than guessing.

Choose interfaces and run the planner.

Power tree & battery life

Per-rail current budget from the verified current-consumption data, rolled up across a duty-cycle scenario into an average draw and battery-life estimate. Built for the low-power, coin-cell world these boards live in.

Run the estimator to see the power tree.

Firmware scaffolding

Generate a Zephyr devicetree overlay and a C pin/address header as bring-up scaffolding seeded from the verified pinout. Bus type, I²C address and pin numbers are datasheet-verified; the board wiring (IRQ GPIO, chip-select, mux) is left as TODO comments to fill in — this is generated from the MPN, not from your schematic.

Generate to see the overlay + header.

Whole-board handoff active workspace project

Generate an I²C board overlay, connectivity pin-map and Kconfig TODOs from the active project. Exact package-pin connectivity is preserved; GPIO controller indexes, chip-selects and unresolved address straps are never guessed.

Choose an active workspace project, then generate.
Engineering calculators

Calculators

Same math as the xERC rules — cited, refuse-to-guess.

ldo_dissipation LDO heat → junction temp

divider standard-value pair for a target Vout

led_resistor indicator LED series R

i2c_rise_time bus rise time vs the mode limits

crystal_load_caps C1/C2 for a spec'd CL

buck_inductor L, ripple window, Isat

trace_width minimum copper for the current

thermal_via_array EP stitch vias → °C/W

All 33 generic JSON form · POST /api/calc/{name}

Catalog loads when this tab opens.
Manufacturing & review

Design analysis

Run the full manufacturing-readiness suite — BOM health, DFM, worst-case (WCCA), compliance, the design-review gate, fab constraints and the BOM export — on a whole project board (every part) or on a single component. These are board-level analyses, so a real multi-part project is the right input. Same engine the API and xERC run.

Pick a component above, choose an analysis, and run it.
Part intelligence

Part data

Everything the pipeline knows about the selected verified component: live sourcing (lifecycle, RoHS/REACH, offers), the e-datasheet export with its conformance check, and the full verified component record with coverage.

Catalog search GET /api/search — filter the verified corpus

Filter the verified catalog and pick a part — selecting one drives every tool below.
Pick a component above and fetch its data.
Statistics & retrieval

Tolerance & search

Monte-Carlo tolerance analysis over a parametric preset (divider output, divider ratio, RC corner) plus the extreme-value bound and spec yield — and a semantic search across the verified component corpus.

Monte-Carlo tolerance POST /api/montecarlo

Set the preset + tolerances and run.

MLCC voltage/temperature derating POST /api/derating

Pick a dielectric + case and check the retained capacitance / voltage margin.

Semantic component search GET /api/vectordb/search

Describe a part in plain language to search the corpus.
Power architecture

Power tree

Build a regulator chain — a source plus buck / boost / LDO stages — and get per-stage loss + efficiency, total input power, and the end-to-end efficiency. Switchers take an efficiency; LDOs are computed from Vin/Vout/Iout (AN761).

Source

Stages

Add stages and analyse.
Project lifecycle

Project docs

Bring an external BOM in (paste CSV → scrubbed + resolved against the verified corpus) and build a requirements traceability matrix (RTM) — coverage per requirement, orphans, and design items nothing traces to.

BOM import POST /api/bom/import

Paste CSV with a header row (e.g. mpn,qty,refdes).

Paste a BOM CSV and import.

Requirements traceability (RTM) POST /api/requirements/rtm

One requirement per line: rid | text | priority (priority optional). Add trace links below as rid → target to mark a requirement implemented/verified.

Enter requirements and build the matrix.
Simulation & generators

Simulation workbench

Configure and inspect a bounded ngspice micro-circuit run. Project context, logical revision, solver capability, artifacts, and claim limits remain visible with the result. A successful run is diagnostic evidence only and never schematic, PCB, or release signoff.

Run setup checking capability…

AnalysisDC operating point · .op
Projectnot selected
Logical revisionnot bound
Circuit sourcemanual structured micro-circuit
Model setprimitive devices; generic diode only
Unbound. Choose a project to record its server-owned logical revision with each run.

One device per line: ref type node1 node2 value. The type must match the reference prefix. Node 0 is ground.

Waiting for a verified capability contract.

Results not run

Enter a supported micro-circuit and run the operating point.

Session run history 0 runs

Runs from this browser tab will appear here. History is not persisted engineering evidence.

Built-in blocks POST /api/blocks/netlist

Pick a block and generate its Design JSON.