Design review (xERC)
Import a board netlist and check it against the verified electrical model of every part — abs‑max vs rail voltage, decoupling, I²C pull‑ups & address collisions, mixed‑voltage nets, current budget, floating supplies. Findings carry their datasheet or engineering basis. Accepts KiCad (.net) and Altium / Protel (.NET) netlists — format auto‑detected.
Scope: xERC evaluates schematic/netlist connectivity, component evidence, and declared constraints. It does not inspect PCB placement, copper geometry, routed return paths, creepage geometry, assembly workmanship, or physical test results; close those with PCB DRC/DFM and test evidence.
Input & configuration
Isolation barriers optional — declare a galvanic boundary so RC-E104 checks it at its RATED working voltage
A netlist cannot prove physical barrier geometry. Declare the two sides, rated working voltage and required grade so the review can derive the required spacing constraint and census bridging parts. Verify the actual clearance/creepage in PCB DRC and the released layout.